The present disclosure relates to a memory access control circuit, and more particularly, to a memory access control circuit, prefetch circuit, memory device and information processing system for gaining burst access to a memory.
A processor uses a memory both as an instruction storage area and as a data storage area. Therefore, it is necessary for the processor to access the memory highly frequently during the execution of a program. In order to reduce the burden on the memory resulting from such frequent accesses, a cache memory is provided between the processor and memory. A cache memory manages a plurality of continuous words as a line. Therefore, the plurality of words are filled altogether at the time of a cache mishit. At this time, a burst transfer is used to transfer data from the memory.
In order to achieve transfer of a plurality of words using a burst transfer, a system is known which can change the sequence of the words to be transferred by using the wraparound function adapted to wrap around the addresses in a specific range. For example, a data processor has been proposed which allows different types of burst transfer such as four-burst wrap (WRAP4), eight-burst wrap (WRAP8) and 16-burst wrap (WRAP16) to be specified (refer, for example, to Japanese Patent Laid-Open No. 2006-155488).